Device leakage current is a problem for many modern circuit designs, such as those implemented with deep sub-micron technology. In particular, device leakage current can significantly reduce or limit the performance of low power circuits, such as battery powered circuits.
One approach to reducing leakage current is to increase the length (e.g., channel length) of devices (e.g., transistors). However, such modifications may impact device performance by providing less drain saturation current for a given device geometry. In addition, larger devices typically require more die area and increased cost.
Another approach to reducing leakage current is to reduce the density of logic circuitry in a given circuit design. However, such changes are not always practical in view of application requirements which may need certain minimum logic operations to be performed.
Yet another approach to reducing leakage current is to work with device manufacturers to increase the efficiency of individual devices. However, such an approach may require cumbersome additional processing steps that are time intensive, expensive, and impractical to develop and verify the effectiveness thereof.
As a result, there is a need for an improved approach to reducing device leakage current that improves upon one or more of the approaches discussed above.